Solid state image sensor and electronic device

ABSTRACT

There is provided a solid state image sensor including a photoelectric conversion unit formed and embedded in a semiconductor substrate, an impurity region that retains an electric charge generated by the photoelectric conversion unit, and a transfer transistor that transfers the electric charge to the impurity region. A gate electrode of the transfer transistor is formed in a depth direction toward the photoelectric conversion unit in the semiconductor substrate, from a surface of the semiconductor substrate on which the impurity region is formed. A channel portion of the transfer transistor is surrounded by the gate electrode in two or more directions other than a direction of the impurity region, as seen from the depth direction.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is divisional application of U.S. patent applicationSer. No. 14/773,269 filed on Sep. 4, 2015, which is a U.S. NationalPhase of International Patent Application No. PCT/JP2014/055008 filed onFeb. 28, 2014, which claims priority benefit of Japanese PatentApplication No. JP 2013-052076 filed in the Japan Patent Office on Mar.14, 2013. Each of the above-referenced applications is herebyincorporated herein by reference in its entirety.

TECHNICAL FIELD

The present technology relates to a solid state image sensor, itsmanufacturing method, and an electronic device, and particularly to asolid state image sensor, its manufacturing method, and an electronicdevice that configure a solid state image sensor tolerant tomisalignment during manufacturing and having a high conversionefficiency of photoelectric conversion.

BACKGROUND ART

In a solid state image sensor (image sensor) using semiconductor (Si), aphoto diode (PD) utilizing p-n junction of semiconductor is known as aphotoelectric conversion element that converts a received light to anelectrical signal. The element utilizing a photo diode is mounted onmany electronic devices, such as a digital camera, a video camera, amonitoring camera, a copy machine, and a facsimile.

In recent years, what is called CMOS solid state image sensor, which ismanufactured by a complementary metal oxide semiconductor (CMOS) processincluding peripheral circuits, is used frequently as the solid stateimage sensor.

In this CMOS solid state image sensor, an electric charge accumulated ineach pixel or each row of photo diode is read, and thus a differenceoccurs between the time periods during which optical charges areaccumulated, which results in a distortion generated on an imagedsubject when the subject is moving. To prevent the distortion of thesubject, a global shutter function for performing light exposuresimultaneously in all pixels is necessary.

As means for configuring the global shutter, there is a mechanicalshutter method that provides a mechanical shutter. This method is amethod in which the light that enters into the solid state image sensoris turned on and off by the mechanical shutter, so that light exposureis performed simultaneously in all pixels. The electric chargeaccumulated in the photo diode is read sequentially in the same way asthe CMOS solid state image sensor of the past.

However, in the mechanical shutter method, the mechanical shutter isnecessary, and thus reduction in size is difficult, and mechanical drivelimits the shutter speed.

Thus, to compensate the drawback of the mechanical shutter method, anelectrical global shutter method is reported (for example, PatentLiteratures 1 to 3). In the electrical global shutter method, theelectric charges accumulated in the photo diode are simultaneously andtransiently transferred to electric charge accumulating parts withrespect to all pixels, and the electric charges accumulated in theelectric charge accumulating parts are read by scanning each rowsequentially.

Here, the electric charge accumulating parts need to be shaded, toprevent the noise due to the photoelectric conversion during the periodfor reading the accumulation electric charges sequentially. Thus, thephoto diode areas in all pixel regions are made smaller by the shadedregion. Also, the electric charge accumulating parts and a pixel circuitunit are arranged close to the front side of the semiconductorsubstrate, there is a problem that the photo diode has a low apertureratio.

To compensate this drawback, for example, Patent Literature 4 proposes adevice that uses the electrical global shutter method and receives lightwith its back side, so that the light amount entering into the photodiode does not decrease by the shading film. Also, in Patent Literature4, the light is prevented from entering into the electric chargeaccumulating part, by forming a shading film functioning as aphotoelectric conversion film at a position close to the back side, toprevent the occurrence of the noise.

However, in the technology disclosed in Patent Literature 4, the photodiode is arranged on a top layer surface (surface) of the back side ofthe semiconductor substrate, and thus the photo diode area is difficultto be arranged.

Thus, for example, Patent Literatures 5, 6 report a technology thatmaximizes the photo diode area by allowing a light to enter from theback side of the semiconductor substrate and embedding the photo diodein the semiconductor.

CITATION LIST Patent Literature

-   Patent Literature 1: JP 2007-503722T-   Patent Literature 2: JP 2006-311515A-   Patent Literature 3: JP 2009-268083A-   Patent Literature 4: JP 2012-004443A-   Patent Literature 5: JP 2005-223084A-   Patent Literature 6: JP 2012-164971A

SUMMARY Technical Problem

FIG. 1 illustrates a pixel structure of a CMOS solid state image sensordescribed in Patent Literature 5.

A pixel 1 of the CMOS solid state image sensor illustrated in FIG. 1 isformed such that a photo diode 3 is embedded in a substrate of a p-typesemiconductor substrate 2. The photo diode 3 includes a p-typesemiconductor region (p+ region) 11 of a high impurity concentrationformed at the front side of the semiconductor substrate 2, and an n-typesemiconductor region 12 consisting of a high concentration impurityregion (n+ region) 12A, which is in contact with the p-typesemiconductor region 11, and a low impurity concentration region (nregion) 12B formed in the depth direction toward the back side of thesemiconductor substrate 2.

Then, at the front side of the semiconductor substrate 2, a gateelectrode 5 of a transfer transistor for transferring electric charge toan n+ region 4 as a floating diffusion region (FD) is embedded in thedepth direction from the substrate surface to the photo diode 3. Theouter periphery of the gate electrode 5 is covered by a gate insulatingfilm 6 such as a silicon dioxide film, for example.

In addition, a pixel separating region 8 and a gate electrode 9 of areset transistor are formed at the front side of the semiconductorsubstrate 2, for example.

The p+ region 11 of the photo diode 3 is formed to maximize the electriccharge capacity for accumulation in the photo diode 3, and a p-typesemiconductor region (p− region) 13 of a lower impurity concentrationthan the p+ region 11 is formed in the vicinity of the gate electrode 5.

In this pixel structure, the electric charge accumulated in the photodiode 3 flows around the gate electrode 5, and creates a potentialbarrier when the p+ region 11 of the high impurity concentration is tooclose to the gate electrode 5 so as to cause a trouble in electriccharge transfer. Thus, this pixel structure is vulnerable to themisalignment between the p+ region 11 of the high impurity concentrationand the gate electrode 5 of the photo diode 3, and therefore it isnecessary to dilute the concentration of the p+ region 11 of the highimpurity concentration, or to arrange the p+ region 11 sufficiently awayfrom the gate electrode 5. However, this makes the saturation electriccharge amount of the photo diode 3 smaller.

Thus, FIGS. 2A and 2B illustrates a pixel structure disclosed in PatentLiterature 6, which is tolerant to the misalignment between the p+region 11 of the high impurity concentration and the gate electrode 5 ofthe photo diode 3.

FIG. 2A illustrates a cross-sectional view of the pixel 1, and FIG. 2 Billustrates a plan view of the pixel 1.

In this pixel structure, the gate electrode 5 is formed in a squareshape, as seen in the depth direction, as illustrated in FIG. 2 B, andthe n+ region 4 is formed as a floating diffusion region (FD) inside thegate electrode 5. Thereby, the electric charge accumulated in the photodiode 3 flows inside the gate electrode 5 of a square shape, and thus istolerant to the misalignment between the p+ region 11 of the highimpurity concentration and the gate electrode 5 of the photo diode 3.

However, since the n+ region 4 as the floating diffusion region (FD) issurrounded by the gate electrode 5, the capacity between the floatingdiffusion region and the gate electrode 5 becomes large, deterioratingthe conversion efficiency for converting the electric charge accumulatedin the floating diffusion region to the output voltage.

The present technology is made in view of the above situation, toconfigure a solid state image sensor that is tolerant to misalignmentduring manufacturing and having a high conversion efficiency ofphotoelectric conversion.

Solution to Problem

A solid state image sensor according to a first embodiment of thepresent technology includes: a photoelectric conversion unit formed andembedded in a semiconductor substrate; an impurity region that retainsan electric charge generated by the photoelectric conversion unit; and atransfer transistor that transfers the electric charge to the impurityregion. A gate electrode of the transfer transistor is formed in a depthdirection toward the photoelectric conversion unit in the semiconductorsubstrate, from a surface of the semiconductor substrate on which theimpurity region is formed. A channel portion of the transfer transistoris surrounded by the gate electrode in two or more directions other thana direction of the impurity region, as seen from the depth direction.

A manufacturing method of a solid state image sensor according to thefirst embodiment of the present technology includes the steps of:forming a photoelectric conversion unit by embedding the photoelectricconversion unit in a semiconductor substrate; forming a gate electrodeof a transfer transistor that transfers an electric charge generated bythe photoelectric conversion unit, in a depth direction toward thephotoelectric conversion unit in the semiconductor substrate, from asurface of the semiconductor substrate; and forming an impurity regionthat retains the electric charge transferred by the transfer transistor,on the surface of the semiconductor substrate. A channel portion of thetransfer transistor is surrounded by the gate electrode in two or moredirections other than a direction of the impurity region, as seen fromthe depth direction.

An electronic device according to the first embodiment of the presenttechnology includes: a solid state image sensor including aphotoelectric conversion unit formed and embedded in a semiconductorsubstrate, an impurity region that retains an electric charge generatedby the photoelectric conversion unit, and a transfer transistor thattransfers the electric charge to the impurity region. A gate electrodeof the transfer transistor is formed in a depth direction toward thephotoelectric conversion unit in the semiconductor substrate, from asurface of the semiconductor substrate on which the impurity region isformed. A channel portion of the transfer transistor is surrounded bythe gate electrode in two or more directions other than a direction ofthe impurity region, as seen from the depth direction.

According to the first embodiment of the present technology, aphotoelectric conversion unit is formed and embedded in a semiconductorsubstrate, a gate electrode of a transfer transistor that transfers anelectric charge generated by the photoelectric conversion unit is formedin a depth direction toward the photoelectric conversion unit in thesemiconductor substrate, from a surface of the semiconductor substrate,and an impurity region that retains the electric charge transferred bythe transfer transistor is formed on the surface of the semiconductorsubstrate. A channel portion of the transfer transistor is surrounded bythe gate electrode in two or more directions other than a direction ofthe impurity region, as seen from the depth direction.

A solid state image sensor according to a second embodiment of thepresent technology includes: a photoelectric conversion unit formed andembedded in a semiconductor substrate; a memory unit that retains anelectric charge generated by the photoelectric conversion unit; atransfer transistor that transfers the electric charge to the memoryunit; and a discharge transistor that discharges an unnecessary electriccharge generated by the photoelectric conversion unit. A gate electrodeof the transfer transistor and a gate electrode of the dischargetransistor are adjacent to each other in parallel in a depth directionof the semiconductor substrate, via an insulating film or an impurityregion having a higher impurity concentration than a channel portionwhich forms an electrical current path.

A manufacturing method of a solid state image sensor according to thesecond embodiment of the present technology includes the steps of:forming a photoelectric conversion unit by embedding the photoelectricconversion unit in a semiconductor substrate; forming a gate electrodeof a transfer transistor that transfers to a memory unit an electriccharge generated by the photoelectric conversion unit, and a gateelectrode of a discharge transistor that discharges an unnecessaryelectric charge generated by the photoelectric conversion unit, inparallel in a depth direction from a surface of the semiconductorsubstrate, toward the photoelectric conversion unit in the semiconductorsubstrate; and forming an insulating film or an impurity region having ahigher impurity concentration than a channel portion which forms anelectrical current path, between the gate electrode of the transfertransistor and the gate electrode of the discharge transistor.

An electronic device according to the second embodiment of the presenttechnology includes: a solid state image sensor including aphotoelectric conversion unit formed and embedded in a semiconductorsubstrate, a memory unit that retains an electric charge generated bythe photoelectric conversion unit, a transfer transistor that transfersthe electric charge to the memory unit, and a discharge transistor thatdischarges an unnecessary electric charge generated by the photoelectricconversion unit. A gate electrode of the transfer transistor and a gateelectrode of the discharge transistor are adjacent to each other inparallel in a depth direction of the semiconductor substrate, via aninsulating film or an impurity region having a higher impurityconcentration than a channel portion which forms an electrical currentpath.

According to the second embodiment of the present technology,photoelectric conversion unit is formed and embedded in a semiconductorsubstrate, a gate electrode of a transfer transistor that transfers to amemory unit an electric charge generated by the photoelectric conversionunit, and a gate electrode of a discharge transistor that discharges anunnecessary electric charge generated by the photoelectric conversionunit are formed in parallel in a depth direction from a surface of thesemiconductor substrate, toward the photoelectric conversion unit, andan insulating film or an impurity region having a higher impurityconcentration than a channel portion which forms an electrical currentpath is formed between the gate electrode of the transfer transistor andthe gate electrode of the discharge transistor.

A solid state image sensor according to a third embodiment of thepresent technology includes: a photoelectric conversion unit formed andembedded in a semiconductor substrate; a memory unit that retains anelectric charge generated by the photoelectric conversion unit; atransfer transistor that transfers the electric charge to the memoryunit; and a discharge transistor that discharges an unnecessary electriccharge generated by the photoelectric conversion unit. End portions,close to the photoelectric conversion unit, of a gate electrode of thetransfer transistor and a gate electrode of the discharge transistor arelocated at adjacent positions in a formation plane of the photoelectricconversion unit. As a depth from a surface of the semiconductorsubstrate becomes shallower, the gate electrode of the transfertransistor and the gate electrode of the discharge transistor graduallyget away from each other.

A manufacturing method of a solid state image sensor according to thethird embodiment of the present technology includes the steps of:forming a photoelectric conversion unit by embedding the photoelectricconversion unit in a semiconductor substrate; and forming a gateelectrode of a transfer transistor that transfers to a memory unit anelectric charge generated by the photoelectric conversion unit, and agate electrode of a discharge transistor that discharges an unnecessaryelectric charge generated by the photoelectric conversion unit, in adepth direction from a surface of the semiconductor substrate, towardthe photoelectric conversion unit in the semiconductor substrate. Endportions, close to the photoelectric conversion unit, of the gateelectrode of the transfer transistor and the gate electrode of thedischarge transistor are located at adjacent positions in a formationplane of the photoelectric conversion unit. As a depth from the surfaceof the semiconductor substrate becomes shallower, the gate electrode ofthe transfer transistor and the gate electrode of the dischargetransistor gradually get away from each other.

An electronic device according to the third embodiment of the presenttechnology includes: a solid state image sensor including aphotoelectric conversion unit formed and embedded in a semiconductorsubstrate, a memory unit that retains an electric charge generated bythe photoelectric conversion unit, a transfer transistor that transfersthe electric charge to the memory unit, and a discharge transistor thatdischarges an unnecessary electric charge generated by the photoelectricconversion unit. End portions, close to the photoelectric conversionunit, of a gate electrode of the transfer transistor and a gateelectrode of the discharge transistor are located at adjacent positionsin a formation plane of the photoelectric conversion unit. As a depthfrom a surface of the semiconductor substrate becomes shallower, thegate electrode of the transfer transistor and the gate electrode of thedischarge transistor gradually get away from each other.

According to the third embodiment of the present technology, aphotoelectric conversion unit is formed and embedded in a semiconductorsubstrate, and a gate electrode of a transfer transistor that transfersto a memory unit an electric charge generated by the photoelectricconversion unit, and a gate electrode of a discharge transistor thatdischarges an unnecessary electric charge generated by the photoelectricconversion unit are formed in a depth direction from a surface of thesemiconductor substrate, toward the photoelectric conversion unit. Endportions, close to the photoelectric conversion unit, of the gateelectrode of the transfer transistor and the gate electrode of thedischarge transistor are located at adjacent positions in a formationplane of the photoelectric conversion unit. As a depth from the surfaceof the semiconductor substrate becomes shallower, the gate electrode ofthe transfer transistor and the gate electrode of the dischargetransistor gradually get away from each other.

The solid state image sensor and the electronic device may be anindependent device, or may be a module built in another device.

Advantageous Effects of Invention

According to the first to third aspect of the present technology, asolid state image sensor that is tolerant to misalignment duringmanufacturing and having a high conversion efficiency of photoelectricconversion is configured.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram illustrating a pixel structure of past of a CMOSsolid state image sensor.

FIGS. 2A and 2B are diagrams illustrating a pixel structure of past of aCMOS solid state image sensor.

FIG. 3 is a block diagram illustrating an exemplary configuration of asolid state image sensor employing the present technology.

FIG. 4 is a diagram illustrating an equivalent circuit of a firstconfiguration of a pixel.

FIG. 5 is a cross-sectional view illustrating a structure of a pixel ofa first configuration.

FIG. 6A is a plan view illustrating a structure of a pixel of a firstconfiguration.

FIGS. 6B, 6C, 6D, and 6E are cross-sectional views illustrating thestructure of the pixel of the first configuration.

FIGS. 7A, 7B, and 7C are diagrams illustrating an exemplary variant of agate electrode shape.

FIG. 8 is a diagram illustrating an equivalent circuit of a secondconfiguration of a pixel.

FIG. 9 is a cross-sectional view illustrating a structure of a pixel ofa second configuration.

FIG. 10 is a plan view illustrating a structure of a pixel of a secondconfiguration.

FIG. 11 is a cross-sectional view illustrating a structure of a pixel ofa third configuration.

FIG. 12 is a plan view illustrating a structure of a pixel of a thirdconfiguration.

FIG. 13 is a cross-sectional view illustrating a structure of a pixel ofa fourth configuration.

FIG. 14 is a plan view illustrating a structure of a pixel of a fourthconfiguration.

FIG. 15 is a cross-sectional view illustrating a structure of a pixel ofa fifth configuration.

FIG. 16 is a plan view illustrating a structure of a pixel of a fifthconfiguration.

FIG. 17 is a cross-sectional view illustrating a structure of a pixel ofa sixth configuration.

FIG. 18 is a plan view illustrating a structure of a pixel of a sixthconfiguration.

FIGS. 19A, 19B, 19C, and 19D are diagrams for describing a manufacturingmethod of a pixel of a third configuration.

FIGS. 20A and 20B are diagrams for describing a manufacturing method ofa pixel of a third configuration.

FIG. 21 is a diagram for describing a manufacturing method of a pixel ofa third configuration.

FIGS. 22A, 22B, and 22C are diagrams for describing anothermanufacturing method of a pixel of a third configuration.

FIGS. 23A, 23B, and 23C are diagrams for describing anothermanufacturing method of a pixel of a third configuration.

FIG. 24 is a cross-sectional view illustrating a structure of a pixel ofa seventh configuration.

FIGS. 25A, 25B, 25C, and 25D are plan views illustrating a structure ofa pixel of a seventh configuration.

FIG. 26 is a cross-sectional view illustrating a structure of a pixel ofa seventh configuration.

FIGS. 27A, 27B, 27C, and 27D are diagrams illustrating an exemplaryvariant of a gate electrode shape.

FIG. 28 is a cross-sectional view illustrating a structure of a pixel ofan eighth configuration.

FIG. 29 is a plan view illustrating a structure of a pixel of an eighthconfiguration.

FIG. 30 is a cross-sectional view illustrating a structure of a pixel ofa ninth configuration.

FIG. 31 is a plan view illustrating a structure of a pixel of a ninthconfiguration.

FIG. 32 is a cross-sectional view illustrating a structure of a pixel ofa tenth configuration.

FIG. 33 is a plan view illustrating a structure of a pixel of a tenthconfiguration.

FIG. 34 is a cross-sectional view illustrating a structure of a pixel ofan eleventh configuration.

FIG. 35 is a cross-sectional view illustrating a structure of a pixel ofa twelfth configuration.

FIG. 36 is a cross-sectional view illustrating a structure of a pixel ofa thirteenth configuration.

FIGS. 37A, 37B, 37C, and 37D are diagrams for describing a manufacturingmethod of a pixel of a seventh configuration.

FIGS. 38A and 38B are diagrams for describing a manufacturing method ofa pixel of a seventh configuration.

FIG. 39 is a diagram for describing a manufacturing method of a pixel ofa seventh configuration.

FIGS. 40A, 40B, and 40C are diagrams for describing a manufacturingmethod of a pixel of a tenth configuration.

FIG. 41 is a block diagram illustrating an exemplary configuration of animage sensing device as an electronic device employing the presenttechnology.

DESCRIPTION OF EMBODIMENTS

In the following, embodiments for carrying out the present technology(hereinafter, referred to as embodiment) will be described. Note that,description will be made in the following order.

1. An overall configuration example of a solid state image sensoremploying the present technology2. First to sixth configurations of a pixel of a solid state imagesensor3. A manufacturing method of a pixel of the third configuration4. Seventh to thirteenth configurations of a pixel of a solid stateimage sensor5. A manufacturing method of a pixel of the seventh configuration6. A manufacturing method of a pixel of the tenth configuration7. An exemplary configuration of an electronic device employing thepresent technology

<Overall Configuration Example of Solid State Image Sensor>

FIG. 3 is a block diagram illustrating an overall configuration exampleof a solid state image sensor employing the present technology.

The solid state image sensor 41 of FIG. 3 includes a timing control unit42, a vertical scanning circuit 43, a pixel array unit 44, a constantelectrical current source circuit unit 45, a reference signal generatingunit 46, a column AD conversion unit 47, a horizontal scanning circuit48, a horizontal output line 49, and an output circuit 50.

The timing control unit 42 supplies a clock signal and a timing signalnecessary for a predetermined operation, to the vertical scanningcircuit 43 and the horizontal scanning circuit 48, on the basis of themaster clock of a predetermined frequency. For example, the timingcontrol unit 42 supplies the timing signal of the shutter operation andthe read operation of the pixels 51, to the vertical scanning circuit 43and the horizontal scanning circuit 48. Also, although not depicted, thetiming control unit 42 supplies the clock signal and the timing signalnecessary for a predetermined operation, to the reference signalgenerating unit 46 and the column AD conversion unit 47 as well.

The vertical scanning circuit 43 sequentially supplies a signal forcontrolling the output of a pixel signal, to the pixels 51 arrayed inthe vertical direction of the pixel array unit 44, at a predeterminedtime.

In the pixel array unit 44, a plurality of pixels 51 are located in atwo-dimensional array manner (matrix manner).

A plurality of pixels 51 located in the two-dimensional array manner areconnected, row by row, to the vertical scanning circuit 43 by thehorizontal signal lines 52. In other words, a plurality of pixels 51located on the same row in the pixel array unit 44 are connected to thevertical scanning circuit 43 by a same horizontal signal line 52.Although, in FIG. 3 , the horizontal signal lines 52 are illustrated asa wired line, it is not limited to one line.

Also, a plurality of pixels 51 located in the two-dimensional arraymanner are connected, column by column, to the horizontal scanningcircuit 48 by the vertical signal lines 53. In other words, a pluralityof pixels 51 located on a same column in the pixel array unit 44 areconnected to the horizontal scanning circuit 48 by a same verticalsignal lines 53.

Each pixels 51 in the pixel array unit 44 outputs a pixel signalaccording to the electric charge accumulated in the inside, to thevertical signal line 53 in accordance with the signal supplied from thevertical scanning circuit 43 via the horizontal signal line 52. Thedetailed configuration of the pixels 51 will be described later withreference to FIG. 4 , for example.

The constant electrical current source circuit unit 45 includes aplurality of load MOSs 54, and one load MOS 54 is connected to onevertical signal line 53. In the load MOSs 54, the bias voltage isapplied to the gate, and the source is grounded, in order to configure asource follower circuit in cooperation with the transistors in thepixels 51 connected via the vertical signal lines 53.

The reference signal generating unit 46 includes a digital to analogconverter (DAC) 46 a, and generates a reference signal of a rampwaveform in response to the clock signal from the timing control unit42, and supplies it to the column AD conversion unit 47.

The column AD conversion unit 47 includes a plurality of analog-digitalconverters (ADC) 25, which is provided one for each column of the pixelarray unit 44. Thus, one vertical signal line 53 is connected to aplurality of pixels 51, one load MOS 54, and one ADC 55.

The ADC 55 performs correlated double sampling (CDS) on the pixel signalsupplied from the pixels 51 of the same column via the vertical signalline 53, and further performs the AD conversion.

Each of ADCs 55 temporarily stores the pixel data after the ADconversion, and outputs it to the horizontal output line 49 inaccordance with the control of the horizontal scanning circuit 48.

The horizontal scanning circuit 48 sequentially outputs the pixel datastored in a plurality of ADCs 55, to the horizontal output line 49 at apredetermined time.

The horizontal output line 49 is connected to the output circuit(amplifier circuit) 50, and the pixel data after AD conversion outputfrom each ADC 55 is output to the outside of the solid state imagesensor 1 from the output circuit 50 via the horizontal output line 49.In some cases, the output circuit 50 performs only buffering forexample, and in other cases various types of digital signal processes,such as black level adjustment and column variation correction, areperformed.

The solid state image sensor 41 configured as described above is a CMOSimage sensor which is referred to as column AD type in which the ADC 55that executes the CDS process and the AD conversion process is providedfor each vertical column.

<First Configuration of Pixel 51>

FIG. 4 illustrates an equivalent circuit of a first configuration of thepixel 51.

The pixel 51 includes a photo diode 61 as a photoelectric conversionelement, a transfer transistor 62, a floating diffusion region (FD) 63,a reset transistor 64, an amplification transistor 65, and a selectiontransistor 66.

The photo diode 61 is a photoelectric conversion unit that generates andaccumulates electric charge (signal electric charge) according to thereceived light amount. In the photo diode 61, the anode terminal isgrounded, and the cathode terminal is connected to the FD 63 via thetransfer transistor 62.

When turned on by a transferred signal TX, the transfer transistor 62reads the electric charge generated by the photo diode 61, and transfersit to the FD 63.

The FD 63 retains the electric charge read from the photo diode 61. Whenturned on by a reset signal RST, the reset transistor 64 resets theelectric potential of the FD 63, by discharging the electric chargeaccumulated in the FD 63 to the constant voltage source VDD.

The amplification transistor 65 outputs a pixel signal according to theelectric potential of the FD 63. That is, the amplification transistor65 configures the load MOS 54 and the source follower circuit as theconstant current source, and the pixel signal indicating a levelaccording to the electric charge accumulated in the FD 63 is output tothe ADC 55 via the selection transistor 66 from the amplificationtransistor 65.

The selection transistor 66 is turned on when the pixel 51 is selectedby the selection signal SEL, and outputs the pixel signal of the pixel51 to ADC 55 via the vertical signal line 53. The transferred signal TX,the reset signal RST, and the selection signal SEL are supplied from thevertical scanning circuit 43 via the horizontal signal line 52 (FIG. 3).

<Cross-Sectional View of Pixel 51 of First Configuration>

FIG. 5 is a cross-sectional view illustrating the structure of the pixel51 of the first configuration illustrated in FIG. 4 .

The pixel 51 is formed such that the photo diode 61 is embedded in thesubstrate of a first conductivity type, for example, p-typesemiconductor substrate 71. The photo diode 61 is configured by a p-typesemiconductor region (p+ region) 81 of the high impurity concentrationformed at the front side of the semiconductor substrate 71, and a secondconductivity type, for example, n-type semiconductor region (n-typesemiconductor region) 82. The n-type semiconductor region 82 isconfigured by an n-type semiconductor region (n+ region) 82A of the highimpurity concentration in contact with the p+ region 81, and an n-typesemiconductor region (n region) 82B of the low impurity concentrationformed in the deeper direction toward the back side of the semiconductorsubstrate 71 than the n-type semiconductor region 82A.

Then, at the front side of the semiconductor substrate 71, an n+ region83 is formed as the FD 63, and a gate electrode 84 of the transfertransistor 62 for transferring the electric charge to the n+ region 83is embedded in the depth direction from the substrate surface to thephoto diode 61 in the semiconductor substrate 71. For example, the gateelectrode 84 of the transfer transistor 62 formed of polysilicon isembedded to the same depth as the p-n junction plane between the p+region 81 and the n+ region 82A of the photo diode 61. Note that thegate electrode 84 of the transfer transistor 62 may be embedded to adeeper position than the p-n junction plane, or a slightly shallowerposition than the p-n junction plane, depending on the concentration ofthe impurity region.

The outer circumference of the gate electrode 84 in the substrate of thetransfer transistor 62 is covered by a gate insulating film 85, such asa silicon dioxide film, for example. In the lower portion of the gateelectrode 84 of the transfer transistor 62, a p-type semiconductorregion (p− region) 86 of a lower impurity concentration than the p+region 81 is formed via the gate insulating film 85.

At the front side of the semiconductor substrate 71, an n+ region 87 isformed as one source-drain region of the reset transistor 64, and the n+region 83 as the FD 63 serves as the other source-drain region of thereset transistor 64 as well. Then, the gate electrode 88 of the resettransistor 64 is formed at the upper portion between the n+ region 87 asone source-drain region of the reset transistor 64 and the n+ region 83as the other source-drain region, via the gate insulating film 85.

The n+ region 83 as the FD 63 is connected to the gate electrode of theamplification transistor 65 via the interconnecting line of theundepicted upper portion, and the n+ region 87 as one source-drainregion of the reset transistor 64 is connected to the constant voltagesource VDD via the interconnecting line of the undepicted upper portion.

At the right side of the drawing which is the opposite side to the n+region 83 as seen from the gate electrode 84 of the transfer transistor62, a separation region 89 for separating each pixel 51 of the pixelarray unit 44 is formed by an insulator such as oxide silicon, forexample.

A flattening film 90 is formed at the back side of the semiconductorsubstrate 71, and a color filter 91 and an on-chip lens (OCL) 92 areformed in this order on the flattening film 90 (the downward directionof the drawing).

The pixel 51 having the above cross-sectional configuration has astructure of type having a back side exposed to light, in which thelight enters from the back side of the semiconductor substrate 71 whichis the downward direction of the drawing.

<Plan View of Pixel 51 of First Configuration>

FIG. 6A is a plan view of the surface of the semiconductor substrate 71on which each transistor of the pixel 51 of the first configuration isformed, seen from upward.

As illustrated in FIG. 6A, the transfer transistor 62 and the resettransistor 64 are formed in a shape that shares the n+ region 83 as onesource-drain region of each.

Also, in another region different from the transfer transistor 62 andthe reset transistor 64 of the pixel 51, the amplification transistor 65and the selection transistor 66 are formed in a shape that shares the n+region 103 as one source-drain region of each. More specifically, theamplification transistor 65 is configured by a gate electrode 102, andan n+ region 101 and an n+ region 103 located at the both sides, and theselection transistor 66 is configured by a gate electrode 104, and an n+region 103 and an n+ region 105 located at the both sides.

Also, FIG. 6 B, FIG. 6 C, and FIG. 6 D are cross-sectional views of thevicinity of the transfer transistor 62 of the pixel 51, which are cutoff by the X-X′ line, the Y-Y′ line, and the Z-Z′ line of FIG. 5 ,respectively.

The transfer transistor 62 serves to connect the photo diode 61 embeddedin the semiconductor substrate 71, with the n+ region 83 formed on thesubstrate surface as the FD 63.

In the cut surface of the Z-Z′ line illustrated in FIG. 6 D, the gateelectrode 84 of the transfer transistor 62 is formed in a U shape tosurround three directions. The outer circumference of the gate electrode84 of the U shape is covered by the gate insulating film 85.

A p-type semiconductor region (the p+ region) 121 of the high impurityconcentration is formed at the upper side and the lower side of thedrawing of the gate electrode 84 via the gate insulating film 85, andthe separation region 89 is formed at the right side of the drawing ofthe gate electrode 84, using an insulator such as oxide silicon, forexample.

Note that all of three directions of the upper side, the lower side, andthe right side of the drawing of the gate electrode 84 via the gateinsulating film 85 may be the p+ region 121 or the separation region 89.

In view of the cut surface of the Y-Y′ line illustrated in FIG. 6 C, then+ region 83 is formed as the FD 63 in the opening direction of the gateelectrode 84 of the U shape. When a predetermined control voltage isapplied to the gate electrode 84 of the transfer transistor 62, achannel portion, which forms the electrical current path, is formed atthe inside of the U shape of the gate electrode 84 formed in the depthdirection. The concentration (p) of the impurity region which forms thechannel portion is lower than the impurity concentration (p+ of the p+region 121) of an outside of the gate electrode 84.

FIG. 6 B is a cross-sectional view of the further upper side than thesubstrate surface on which the n+ region 83 is formed as the FD 63. Asillustrated in FIG. 6 B, at the upper side than the substrate surface,the gate electrode 84 is formed in the shape that covers the channelportion inside the U shape as well.

Note that, as illustrated in FIG. 6 E, the gate electrode 84 may beformed in the U shape, in the same way as the substrate inside, at theupper side than the substrate surface as well.

As above, the gate electrode 84 of the transfer transistor 62 is formedin the depth direction in the U shape, as seen from the depth direction,so that the channel portion which forms the electrical current pathcontacts the gate electrode 84 via the gate insulating film 85 fromthree directions, improving the controllability of the electric fieldand performing the transfer of the electric charge smoothly.

In particular, even when the p+ region 81 formed at the upper portion ofthe photo diode 61 is formed at the vicinity of the gate electrode 84 asillustrated in FIG. 5 , the electric charge converted photoelectricallyby the modulation effect by the gate electrode 84 of the U shape iscarried efficiently to the n+ region 83 which is the FU 63.

Thus, even if a misalignment occurred between the p+ region 81 and thegate electrode 84 formed at the upper portion of the photo diode 61 inthe manufacture procedure of the solid state image sensor 41, robusttransfer would be achieved.

Also, there is no concern about the misalignment between the p+ region81 and the gate electrode 84, and therefore the impurity concentrationof the p+ region 81 is made high, and the saturation electric chargeamount is increased by enlarging the p-n junction capacity value of thephoto diode 61.

<Exemplary Variant of Gate Electrode Shape>

FIG. 7A to FIG. 7 C illustrate exemplary variants of the shape of thegate electrode 84 of the transfer transistor 62. Note that each of FIG.7A to FIG. 7 C is the cross-sectional view when cutting off by the Y-Y′line of FIG. 5 , in the same way as FIG. 6 C.

In FIG. 7A, the width of one direction to which the gate electrode 84 ofthe U shape opens is made narrower than the shape illustrated in FIG. 6C. As described above, the opening width of the gate electrode 84 ismade narrow, to further improve the potential controllability of thechannel portion, and further weaken the effect of the potential barrierformation by the p+ region 81 of the photo diode 61, therebytransferring the electric charge stably.

Also, in FIG. 7 B, the gate electrode 84 of the transfer transistor 62does not have the U shape surrounding three directions, but opens at then+ region 83, which is the FD 63, and the separation region 89, to forma “=” shape that include two parallel plate. In this case, the potentialcontrollability of the channel portion is slightly inferior to the Ushape, but the manufacturability improves because of the simple shape ofthe gate electrode 84.

The gate electrode 84 of FIG. 7 C is formed such that two plateinterval, same as FIG. 7 B, is wide in the n+ region 83 which is the FD63 and is narrow in the separation region 89, so as to arrange in afunnel-like shape. In this case as well, the separation region 89 isclosed by the gate electrode 84, and the n+ region 83 is opened, andtherefore the controllability of the electric field increases,performing the transfer of the electric charge smoothly.

Note that the flat surface shape of the gate electrode 84 of thetransfer transistor 62 as seen from the depth direction is not limitedto the U shape illustrated in FIGS. 6C, 6D, and 6E and the shapesillustrated in FIG. 7A to FIG. 7 C, but may be a shape that opens towardthe n+ region 83 which is the FD 63 at least, and the potentialcontrollabilities of other three directions are higher than that of theopening side.

Also, the upper side than the substrate surface correspond to the crosssection of the X-X′ line of FIG. 5 may have the same shape as the shapein the substrate illustrated in FIG. 7A to FIG. 7 C, or the shape thatcovers the channel portion as illustrated in FIG. 6 B.

<Second Configuration of Pixel 51>

FIG. 8 illustrates an equivalent circuit of the second configuration ofthe pixel 51.

The pixel 51 illustrated in FIG. 8 illustrates a pixel configuration forrealizing the electronic global shutter function. Note that, in FIG. 8 ,parts corresponding to FIG. 4 are denoted with the same reference signs,and their description will be omitted as appropriate.

As compared to the above pixel 51 of the first configuration, the pixel51 of the second configuration further includes another transfertransistor 67 for transferring the electric charge, and the memory unit(MEM) 68 that temporarily retains the electric charge beforetransferring the electric charge to the FD 63, between the transfertransistor 62 and the FD 63. In the following, the transfer transistor62 is referred to as the first transfer transistor 62, and the transfertransistor 67 is referred to as the second transfer transistor 67.

Also, in the pixel 51 of the second configuration, the photo diode 61 isnewly connected to the discharge transistor 69 for discharging theunnecessary electric charge.

The operation of the pixel 51 of FIG. 8 will be described briefly.

First, before starting the light exposure, a discharge signal OFG ofhigh level is supplied to the discharge transistor 69 to turn on thedischarge transistor 69, and the electric charge accumulated in thephoto diode 61 is discharged to the constant voltage source VDD to resetthe photo diode 61.

When the discharge transistor 69 is turned off by the discharge signalOFG of low level after the reset of the photo diode 61, the lightexposure is started at all pixels.

When a predetermined light exposure time set in advance is elapsed, thefirst transfer transistor 62 is turned on by the first transferredsignal TX1, and the electric charge accumulated in the photo diode 61 istransferred to the memory unit 68, in all pixels of the pixel array unit44.

After the first transfer transistor 62 is turned off, the row unit readsout the electric charge retained in the memory unit 68 of each pixel 51to the ADC 55 sequentially. The read operation is same as the abovefirst configuration, and the second transfer transistor 67 of the pixel51 of the read row is turned on by the second transferred signal TX2,and the electric charge retained in the memory unit 68 is transferred tothe FD 63. Then, the selection transistor 66 is turned on by theselection signal SEL, so that a signal indicating the level according tothe electric charge accumulated in the FD 63 is output to the ADC 55 viathe selection transistor 66 from the amplification transistor 65.

<Cross-Sectional View of Pixel 51 of Second Configuration>

FIG. 9 is a cross-sectional view illustrating the structure of the pixel51 of the second configuration illustrated in FIG. 8 .

In each drawing in or after FIG. 9 as well, parts corresponding to theabove diagram are denoted with the same reference signs, and theirdescription will be omitted as appropriate.

In the cross-sectional view of the pixel 51 of FIG. 9 , on the substratesurface of the p-type semiconductor substrate 71, the memory unit 68 isformed between the gate electrode 84 of the first transfer transistor 62and the n+ region 83 as one source-drain region of the second transfertransistor 67.

The memory unit 68 is formed in the n-type semiconductor region (the n+region) 141 of the high impurity concentration which accumulates theelectric charge, and the p-type layer 142 for reducing the dark currentis formed on the top face.

Also, at the opposite side to the side at which the first transfertransistor 62 of the memory unit 68 is located, the gate electrode 143of the second transfer transistor 67 is formed on the substrate surfacevia the gate insulating film 144.

At the opposite side to the memory unit 68 of the second transfertransistor 67, the n+ region 83 is formed as the FD 63.

At another region of the upper side of the photo diode 61 where the gateelectrode 84, the memory unit 68, the second transfer transistor 67, andthe n+ region 83 as the FD 63 of the first transfer transistor 62 arenot formed, a gate electrode 145 of the discharge transistor 69 isembedded to the same depth as the p-n junction plane of the photo diode61 in the same way as the gate electrode 84 of the first transfertransistor 62.

The outer circumference of the gate electrode 145 in the substrate ofthe discharge transistor 69 is covered by the gate insulating film 146,such as the silicon dioxide film, for example. At the lower portion ofthe gate electrode 145 of the discharge transistor 69, the p-typesemiconductor region (the p− region) 86 of a lower impurityconcentration than the p+ region 81 is formed via the gate insulatingfilm 146.

An n+ region 147 as one source-drain region of the discharge transistor69 is formed on the surface of the semiconductor substrate 71 of theleft side in the drawing of the gate electrode 145 of the dischargetransistor 69. Also, at the opposite side to the n+ region 147 of thegate electrode 145 of the discharge transistor 69, a separation region148 is formed by the insulator, such as the oxide silicon for example.

The shape of the gate electrode 145 of the discharge transistor 69 asseen from the depth direction is a U shape in the same way as the shapeof the gate electrode 84 of the first transfer transistor 62 illustratedin FIG. 6 B to FIG. 6 D. Also, the periphery in the plan view directionof the gate electrode 145 of the discharge transistor 69 is formed inthe p+ region 121 and the separation region 148, in the same way as thegate electrode 84 of the first transfer transistor 62.

<Plan View of Pixel 51 of Second Configuration>

FIG. 10 is the plan view of the substrate surface on which eachtransistor of the pixel 51 of the second configuration is formed, asseen from upward.

As illustrated in FIG. 10 , in a predetermined region of the pixel 51,the first transfer transistor 62, the memory unit 68, the secondtransfer transistor 67, and the n+ region 83 as the FD 63 are located injuxtaposition.

Also, in another region of the pixel 51, the gate electrode 145 of thedischarge transistor 69, the n+ region 147 which is one of thesource-drain regions, and the separation region 148 are located.

Further, in another region of the pixel 51, the selection transistor 66,the amplification transistor 65, and the reset transistor 64 are locatedin juxtaposition, sharing one source-drain region with another adjacenttransistor. More specifically, the selection transistor 66 is configuredby the gate electrode 162, and the n+ region 161 and the n+ region 163located at the both sides, and the amplification transistor 65 isconfigured by the gate electrode 164, and the n+ region 163 and the n+region 165 located at the both sides, and the reset transistor 64 isconfigured by the gate electrode 166, and the n+ region 165 and the n+region 167 located at the both sides.

<Third Configuration of Pixel 51>

FIG. 11 is a cross-sectional view illustrating the third configurationof the pixel 51.

The pixel structure of the pixel 51 of the third configurationillustrated in FIG. 11 is different in that the shading film 181 isformed in a predetermined region of the layer in which the flatteningfilm 90 is formed, as compared to the pixel structure of the secondconfiguration illustrated in FIG. 9 . Also, the separation region 148between the gate electrode 145 of the discharge transistor 69 and the n+region 83 as the FD 63 is omitted.

FIG. 12 is a plan view of the pixel 51 of, the third configurationillustrated in the same way as FIG. 10 .

When the pixel 51 of the third configuration is seen from the plan viewdirection, the shading film 181 is arranged in the shape that covers thememory unit 68 and the first transfer transistor 62, as illustrated inFIG. 12 . Thereby, the light that enters into the memory unit 68 isblocked, and the noise contamination is reduced while accumulating theelectric charge.

<Fourth Configuration of Pixel 51>

FIG. 13 is a cross-sectional view illustrating the fourth configurationof the pixel 51.

As compared to the pixel structure of the second configurationillustrated in FIG. 9 , the pixel structure of the pixel 51 of thefourth configuration illustrated in FIG. 13 is such that the p-typelayer 142 formed at the upper portion of the n+ region 141 thatfunctions as the memory unit 68 is omitted, and instead the gateelectrode 201 made of polysilicon for example is formed via the gateinsulating film 202. Also, the separation region 148 between the gateelectrode 145 of the discharge transistor 69 and the n+ region 83 as theFD 63 is omitted.

Although, in the pixel structure illustrated in FIG. 13 , the shadingfilm 181 is not formed in the layer in which the flattening film 90 isformed, the shading film 181 may be located in the same way as FIG. 11 .

FIG. 14 is a plan view of the pixel 51 of the fourth configurationillustrated in the same way as FIG. 10 .

When the pixel 51 of the fourth configuration is seen in the plan viewdirection, the gate electrode 201 is located at the upper portion of thememory unit 68, as illustrated in FIG. 14 .

While the memory unit 68 is accumulating the electric charge, thenegative electric potential is applied to the gate electrode 201, toreduce the dark current that occurs in the memory unit 68.

<Fifth Configuration of Pixel 51>

FIG. 15 is a cross-sectional view illustrating the fifth configurationof the pixel 51.

The pixel structure of the pixel 51 of the fifth configurationillustrated in FIG. 15 is different in that the gate electrode 84 of thefirst transfer transistor 62 in FIG. 13 is integrated with the gateelectrode 201 for applying the negative electric potential to the memoryunit 68, as compared to the pixel structure of the fourth configurationillustrated in FIG. 13 . That is, the gate electrode 221 of the firsttransfer transistor 62 of the pixel 51 of the fifth configuration isformed to the upper portion of the memory unit 68, and functions as thegate electrode for applying the negative electric potential to thememory unit 68. Also, in the same way, the gate insulating film 222 ofthe lower portion of the gate electrode 221 is formed such that the gateinsulating film 85 in FIG. 13 is integrated with the gate insulatingfilm 202. Thereby, the control line for applying the negative electricpotential to the gate electrode 201 is omitted in FIG. 13 .

Note that, in the pixel structure illustrated in FIG. 15 , the shadingfilm 181 for shading the memory unit 68 may be located in the layer inwhich the flattening film 90 is formed, in the same way as FIG. 11 .

FIG. 16 is a plan view of the pixel 51 of the fifth configuration,illustrated in the same way as FIG. 14 .

When the pixel 51 of the fifth configuration is seen from the plan viewdirection, the gate electrode 221 of the transfer transistor 62 islocated to the upper portion of the memory unit 68, as illustrated inFIG. 16 .

Thereby, while the memory unit 68 is accumulating the electric charge,the negative electric potential is applied to the gate electrode 221, toreduce the dark current that occurs in the memory unit 68.

<Sixth Configuration of Pixel 51>

FIG. 17 is a cross-sectional view illustrating the sixth configurationof the pixel 51.

The pixel structure of the pixel 51 of the sixth configurationillustrated in FIG. 17 is such that the n region 82B in FIG. 11 isomitted, and a photoelectric conversion film 241 is newly formed in thesubstrate back side direction from and the n+ region 82A, as compared tothe pixel structure of the third configuration illustrated in FIG. 11 .Also, the photoelectric conversion film 241 of each pixel 51 isseparated by a p-type semiconductor region (the p+ region) 242 of thehigh impurity concentration.

The photoelectric conversion film 241 may be compound semiconductor ofChalcopyrite structure or organic material. The compound semiconductorof the Chalcopyrite structure is, for example, CuInSe2, the one made ofCu—Al—Ga—In—S—Se based mixed crystal, and the one made ofCu—Al—Ga—In—S—Se based mixed crystal. Also, a group III or group IVcompound semiconductor layer may be formed. Also, as the organicmaterial, a quinacridone based or coumarin based material may be used,for example. The above materials just illustrate examples of thematerial that can be used for the photoelectric conversion film 241, andis not limited thereto, as long as having a larger light absorptioncoefficient than the semiconductor substrate 71 (silicon). Thephotoelectric conversion film 241 having a larger light absorptioncoefficient than the semiconductor substrate 71 functions as a shadingfilm for shading the visible light.

The n-type semiconductor region (the n+ region) 82A of the high impurityconcentration accumulates the electric charge obtained by thephotoelectric conversion of the photoelectric conversion film 241.

FIG. 18 illustrates a plan view of the pixel 51 of the sixthconfiguration, and is same as the plan view illustrated in FIG. 12 ,except that the shading film 181 is not located.

<Manufacturing Method of Pixel 51 of Third Configuration>

Next, with reference to FIGS. 19A, 19B, 19C, and 19D to FIG. 21 , themanufacturing method of the pixel 51 of the third configurationillustrated in FIG. 11 will be described.

First, as illustrated in FIG. 19A, the photo diode 61 consisting of thep+ region 81 and the n-type semiconductor region 82 is formed in thep-type semiconductor substrate 71. The n-type semiconductor region 82 isconfigured by the n+ region 82A that is close to the p+ region 81 andthe n region 82B that is close to the back side of the semiconductorsubstrate 71.

Although, in the present embodiment, the p-type semiconductor substrate71 is used, it may be such that a p-type well region (P-Well) is formedin the n-type semiconductor substrate, using the n-type semiconductorsubstrate, and the photo diode 61 is formed in the well region.

Thereafter, as illustrated in FIG. 19 B, after the p-type silicon layerof approximately 0.5 to 1.5 μm is formed on the photo diode 61 byepitaxial growth, the separation region 89 is formed by an insulator,such as oxide silicon at a predetermined position which forms theboundary of each pixel 51.

Thereafter, as illustrated in FIG. 19 C, respective gate electrodes ofthe first transfer transistor 62, the second transfer transistor 67, andthe discharge transistor 69 are formed on the substrate surface.

Specifically, the p-type layer of the upper side than the photo diode 61in the region in which the first transfer transistor 62 and thedischarge transistor 69 are formed is etched by the dry etching methodto be removed. Then, ion of p-type, such as boron, for example is doped,at the part which forms the bottom face of the removed region, to formthe p− region 86. Further, after the gate insulating film 85 and thegate insulating film 146 are formed with a silicon dioxide film or thelike on the inner wall of the etched and removed region, the polysiliconis embedded to form the gate electrode 84 of the first transfertransistor 62 and the gate electrode 145 of the discharge transistor 69.

Also, the gate electrode 143 of the second transfer transistor 67 andothers are formed simultaneously.

Thereafter, as illustrated in FIG. 19 D, for example, the source-drainregion of each transistor such as the n+ region 147 of the dischargetransistor 69, the n+ region 83 as the FD 63, the n+ region 141 as thememory unit 68, and the p-type layer 142 on the top face of the n+region 141 are formed on the surface of the semiconductor substrate 71.

Thereafter, as illustrated in FIG. 20A, a connection wire layer 303including a plurality of interlayer films 301 and a plurality of metallines 302 made of tungsten, aluminium, or the like is formed at thefront side of the semiconductor substrate 71.

Then, as illustrated in FIG. 20 B, after a support substrate 304 ispasted at the upper portion of the connection wire layer 303, the backside of the semiconductor substrate 71 is polished to make the depth tothe photo diode 61 at approximately 1 μm to 5 μm, in order to make it athin film.

Thereafter, as illustrated in FIG. 21 , the shading film 181, theflattening film 90, the color filter 91, and the on-chip lens (OCL) 92are formed in this order, at the thinned back side of the semiconductorsubstrate 71.

The pixel 51 of the third configuration is produced by the aboveprocesses.

<Another Manufacturing Method of Pixel 51 of Third Configuration>

With reference to FIGS. 22A, 22B, 22C, 23A, 23B, and 23C, anothermanufacturing method of the gate electrode 84 of the first transfertransistor 62 and the gate electrode 145 of the discharge transistor 69,which are embedded gate electrodes in the pixel, 51 will be described.

First, in the same way as the above manufacturing method, as illustratedin FIG. 22A, the photo diode 61 is formed in the p-type semiconductorsubstrate 71, and thereafter the p-type silicon layer is formed by theepitaxial growth.

Thereafter, as illustrated in FIG. 22 B, the p-type layer of the regionin which the first transfer transistor 62 and the discharge transistor69 are formed is etched by the dry etching method to be removed. In thiscase, as illustrated in the plan view of FIG. 22 C, the p-type layer ofthe semiconductor substrate 71 is etched to the p-n junction plane ofthe photo diode 61 to form a U shape with an unremoved channel part 321of the first transfer transistor 62. In the same way, the dischargetransistor 69 is etched to the p-n junction plane of the photo diode 61to form a U shape with an unremoved channel part 322.

Subsequently, as illustrated in FIG. 23A, the ion of p-type, such asboron for example, is doped in the region etched in the U shape at thepart corresponding to the first transfer transistor 62 and the dischargetransistor 69, in order to form the p− region 86. In this case, aphotoresist is used in the region other than the part where the ion isdoped, without doping the ion d.

Thereafter, as illustrated in FIG. 23 B, the gate insulating film 85 andthe gate insulating film 146 are formed on the surface of the channelpart 321 of the first transfer transistor 62 and the surface of thechannel part 322 of the discharge transistor 69, using the thermaloxidation method or the deposition method, and thereafter the gateelectrode 84 of the first transfer transistor 62 and the gate electrode145 of the discharge transistor 69, which are made of polysilicon, arefurther formed.

As illustrated in the plan view of FIG. 23 C, the channel part 321 ofthe first transfer transistor 62, and the polysilicon other than thepart surrounding the channel part 322 of the discharge transistor 69 areremoved by the dry etching, to completely form the gate electrode 84 ofthe first transfer transistor 62 and the gate electrode 145 of thedischarge transistor 69.

As described above, the gate electrode 84 of the first transfertransistor 62 and the gate electrode 145 of the discharge transistor 69,which are the embedded gate electrodes, are produced. Othermanufacturing method of the pixel 51 is same as the method describedwith reference to FIGS. 19A, 19B, 19C, and 19D to FIG. 21 .

Each of the first to sixth configurations of the pixel 51 in the abovesolid state image sensor 41 is shaped such that the accumulating portionof the electric charge transfer destination is open in one direction,and the potential controllability of other three directions is moreenhanced than the opening side. For example, the gate electrode 84 ofthe first transfer transistor 62 forms a U shape that opens the n+region 83 which is the FD 63, and is embedded in the depth direction.This configures the solid state image sensor tolerant to misalignmentduring manufacturing and having a high conversion efficiency ofphotoelectric conversion.

<Another Problem of Solid State Image Sensor>

In the meantime, when the pixel structure has two transfer routes of theelectric charge accumulated in the photo diode 61, the next problem isconcerned.

In general, the transfer transistor needs to be located at a positionwhere the energy is lowest for the carrier. Thus, when the pixel 51includes the discharge transistor 69 as the transfer transistor thatreads the electric charge from the photo diode 61 in addition to thefirst transfer transistor 62, each of the first transfer transistor 62and the discharge transistor 69 needs to be located at a position wherethe energy is lowest for the carrier, i.e., at a position where theelectric potential is highest in the configuration of the above photodiode 61.

<Cross-Sectional View of Pixel 51 of Seventh Configuration>

Thus, FIG. 24 is a cross-sectional view illustrating the seventhconfiguration of the pixel 51 which is the structure in view of thecarrier energy.

In the drawings in or after FIG. 24 , parts corresponding to the aboveconfiguration are denoted with the same reference signs, and theirdescription will be omitted as appropriate.

In the pixel 51 of FIG. 24 , the location and the shape of the gateelectrodes of the first transfer transistor 62 and the dischargetransistor 69 are different from the above configuration.

More specifically, the gate electrode 341 of the first transfertransistor 62 is embedded to the same depth as the p-n junction plane ofthe photo diode 61 via the gate insulating film 342, like a rod. Also,the gate electrode 343 of the discharge transistor 69, is embedded tothe same depth as the p-n junction plane of the photo diode 61 via thegate insulating film 344, like a rod. Then, the gate electrode 341 ofthe first transfer transistor 62 and the gate electrode 343 of thedischarge transistor 69 are located adjacent to the center portion ofthe photo diode 61.

In the process for forming the photo diode 61, the carrier energybecomes lowest around the p-n junction of the center portion of thephoto diode 61, when the ion is doped uniformly in the creation regionof the photo diode 61 in the plan view direction. Hence, in the seventhconfiguration illustrated in FIG. 24 , the gate electrode 341 of thefirst transfer transistor 62 and the gate electrode 343 of the dischargetransistor 69 are located at the center portion of the photo diode 61,adjacent to each other.

Then, the memory unit 68 as the electric charge transfer destination ofthe first transfer transistor 62 is formed at the left side of the firsttransfer transistor 62 in the drawing. On the other hand, the n+ region147 as the electric charge transfer destination of the dischargetransistor 69 is formed at the right side of the discharge transistor69.

The p-type semiconductor region (the p+ region) 345 of the impurityconcentration higher than the impurity region (p region) which forms thechannel portion is formed between the gate electrode 341 of the firsttransfer transistor 62 and the gate electrode 343 of the dischargetransistor 69, in order to prevent the electric charge from beingexchanged between the two transistors.

<Plan View of Pixel 51 of Seventh Configuration>

FIG. 25A is a plan view of the substrate surface on which eachtransistor of the pixel 51 of the seventh configuration is formed, whichis seen from upward.

As illustrated in FIG. 25A, the gate electrode 341 of the first transfertransistor 62 and the gate electrode 343 of the discharge transistor 69are located at the closest position in the plane in which the photodiode 61 is formed, so as to sandwich the p+ region 345.

As seen from (the n+ region 141 of) the memory unit 68 at the lower sideof the p-type layer 142, the gate electrode 143 of the second transfertransistor 67 and the n+ region 83 as the source-drain region arelocated at the opposite side to the gate electrode 341 of the firsttransfer transistor 62. (the n+ region 141 of) the memory unit 68 andthe n+ region 83 as one source-drain region of the second transfertransistor 67 are shaded by the shading film 181.

In another region of the pixel 51, the selection transistor 66, theamplification transistor 65, and the reset transistor 64 are located injuxtaposition, sharing one source-drain region with another adjacenttransistor. More specifically, the selection transistor 66 is configuredby the gate electrode 162, and the n+ region 161 and the n+ region 163located at the both sides, and the amplification transistor 65 isconfigured by the gate electrode 164, and the n+ region 163 and the n+region 165 located at the both sides, and the reset transistor 64 isconfigured by the gate electrode 166, and the n+ region 165 and the n+region 167 located at the both sides.

Also, FIG. 25 B, FIG. 25 C, and FIG. 25 D are cross-sectional views ofthe vicinity of the first transfer transistor 62 and the dischargetransistor 69 of the pixel 51, which are cut off by the X-X′ line, theY-Y′ line, and the Z-Z′ line of FIG. 24 , respectively.

In the above first to sixth configuration, in contrast to the U shape ofthe gate electrode seen in the depth direction, the gate electrode 341of the first transfer transistor 62 is formed in a rectangular shape andembedded in the depth direction, as understood from the cross-sectionalviews of FIG. 25 B, FIG. 25 C, and FIG. 25 D. The gate electrode 343 ofthe discharge transistor 69 is also formed in a rectangular shape andembedded in the depth direction in the same way.

As illustrated in FIG. 25 C, the p-type semiconductor region (the p+region) 362 of the high impurity concentration is formed at the upperside and the lower side of the drawing of the gate electrode 341 of thefirst transfer transistor 62, via the gate insulating film 342. Also,the p-type semiconductor region (the p+ region) 362 of the high impurityconcentration is formed at the upper side and the lower side of thedrawing of the gate electrode 343 of the discharge transistor 69, viathe gate insulating film 344.

As described above, in the seventh configuration, the gate electrode 341of the first transfer transistor 62 and the gate electrode 343 of thedischarge transistor 69, which are embedded like a rod, are located inparallel and adjacent to each other, at the part at which the carrierenergy becomes lowest (the position at which the electric potential ishighest in the present working example) in the flat surface region wherethe photo diode 61 is formed.

Thereby, the electric charge is transferred efficiently, when theelectric charge is transferred to the memory unit 68 of the n+ region141 by the first transfer transistor 62, and when transferred to the n+region 147 by the discharge transistor 69.

Note that, in the configuration illustrated in FIG. 24 , the p-typesemiconductor region (the p+ region) 345 of the high impurityconcentration is formed between the gate electrode 341 of the firsttransfer transistor 62 and the gate electrode 343 of the dischargetransistor 69.

However, as illustrated in FIG. 26 , instead of the p+ region 345, theseparation region 361 made of an insulating film, such as a silicondioxide film, may be formed between the gate electrode 341 of the firsttransfer transistor 62 and the gate electrode 343 of the dischargetransistor 69.

<Exemplary Variant of Gate Electrode Shape>

FIGS. 27A, 27B, 27C, and 27D illustrates an exemplary variant of theshapes of the gate electrode 341 of the first transfer transistor 62 andthe gate electrode 343 of the discharge transistor 69.

Note that FIG. 27A is a cross-sectional view near the first transfertransistor 62 and the discharge transistor 69 of the pixel 51, and FIG.27 B to FIG. 27 D are cross-sectional views cut off by the X-X′ line,the Y-Y′ line, and the Z-Z′ line of FIG. 27 A.

The shape of the gate electrode illustrated in FIG. 27 in the plan viewdirection is formed in a U shape in the same way as the above first toseventh configurations.

That is, the gate electrode 341 of the first transfer transistor 62 isformed in the U shape that opens toward the n+ region 141 of the leftside in the drawing which is the transfer destination. The gateelectrode 343 of the discharge transistor 69 is formed in the U shapethat opens toward the n+ region 147 of the right side in the drawingwhich is the transfer destination.

By employing this configuration, the electric charge is transferredefficiently, when transferred to the memory unit 68 of the n+ region141, and when transferred to the n+ region 147, and the solid stateimage sensor tolerant to misalignment during manufacturing and having ahigh conversion efficiency of photoelectric conversion is configured.

Note that the shapes of the gate electrode 341 of the first transfertransistor 62 and the gate electrode 343 of the discharge transistor 69is not limited to the U shape, but may employ various types of shapesillustrated in FIG. 7 . That is, the shapes of the gate electrode 341 ofthe first transfer transistor 62 and the gate electrode 343 of thedischarge transistor 69 may employ a shape that opens toward onedirection of the accumulating portion of the electric charge transferdestination to increase the potential controllability of other threedirections relative to the opening side.

<Eighth Configuration of Pixel 51>

FIG. 28 is a cross-sectional view illustrating the eighth configurationof the pixel 51. Also, FIG. 29 is a plan view illustrating the eighthconfiguration of the pixel 51.

In the eighth configuration of the pixel 51, the p-type layer 142 formedat the upper portion of the n+ region 141 that functions as the memoryunit 68 is omitted from the seventh configuration illustrated in FIGS.24 and 25 , and instead the gate electrode 201 made of polysilicon forexample is formed via the gate insulating film 202, in the same way asFIG. 13 .

While the memory unit 68 is accumulating the electric charge, thenegative electric potential is applied to the gate electrode 201, toreduce the dark current that occurs in the memory unit 68.

<Ninth Configuration of Pixel 51>

FIG. 30 is a cross-sectional view illustrating the ninth configurationof the pixel 51. Also, FIG. 31 is a plan view illustrating the ninthconfiguration of the pixel 51.

The pixel structure of the pixel 51 of the ninth configurationillustrated in FIGS. 30 and 31 is different in that the gate electrode341 of the first transfer transistor 62 in FIG. 28 is integrated withthe gate electrode 201 for applying the negative electric potential tothe memory unit 68, as compared to the pixel structure of the eighthconfiguration illustrated in FIGS. 28 and 29 . That is, the gateelectrode 381 of the first transfer transistor 62 of the pixel 51 of theninth configuration is formed to the upper portion of the memory unit68, and functions as the gate electrode for applying the negativeelectric potential to the memory unit 68. Also, in the same way, thegate insulating film 382 located at the lower portion of the gateelectrode 381 is formed such that the gate insulating film 342 in FIG.28 is integrated with the gate insulating film 202. Thereby, the controlline for applying the negative electric potential to the gate electrode201 is omitted in FIG. 30 .

<Tenth Configuration of Pixel 51>

FIG. 32 is a cross-sectional view illustrating the tenth configurationof the pixel 51. Also, FIG. 33 is a plan view illustrating the tenthconfiguration of the pixel 51.

The pixel structure of the pixel 51 of the tenth configurationillustrated in FIGS. 32 and 33 is different in that the gate electrode401 of the first transfer transistor 62 and the gate electrode 403 ofthe discharge transistor 69 are shaped in a V-shaped gate structure, ascompared to the pixel structure of the seventh configuration illustratedin FIGS. 24 and 25 . In more detail, the gate electrode 401 of the firsttransfer transistor 62 and the gate electrode 403 of the dischargetransistor 69 are located at a same location at the bottom of thevicinity of the photo diode 61, but are formed diagonally so as togradually get away as the depth becomes shallower from the surface ofthe semiconductor substrate 71.

The gate insulating film 402 located at the lower portion of the gateelectrode 401 of the first transfer transistor 62, and the gateinsulating film 40 located at the lower portion of the gate electrode403 of the discharge transistor 69 4 are also formed diagonally in thesame way.

In the plan view of FIG. 33 , the p-type semiconductor region (the p+region) 86 of the high impurity concentration is formed at the upperside and the lower side in the drawing of the gate electrode 401 of thefirst transfer transistor 62 and the gate electrode 403 of the dischargetransistor 69.

According to this pixel structure, as understood from the plan view ofFIG. 33 , the gate electrode 401 and the film forming region of the gateinsulating film 402 are arranged spaciously as seen from upward, and itis needless to form the gate insulating film 402 on the side face (theside wall) of a hole formed vertically and to embed the polysilicon(gate electrode 401), and therefore the manufacture of the pixel 51 ismade easy.

<Eleventh Configuration of Pixel 51>

FIG. 34 is a cross-sectional view illustrating the eleventhconfiguration of the pixel 51.

In the pixel structure of the pixel 51 of the eleventh configurationillustrated in FIG. 34 , the gate electrode 411 of the first transfertransistor 62 is formed to the upper portion of the memory unit 68 andfunctions as the gate electrode for applying the negative electricpotential to the memory unit 68, as compared to the tenth configurationillustrated in FIG. 32 .

Also, the gate insulating film 412 located at the lower portion of thegate electrode 411 is formed to the upper portion of the memory unit 68in the same way. Thereby, while the memory unit 68 is accumulating theelectric charge, the negative electric potential is applied to the gateelectrode 411, to reduce the dark current that occurs in the memory unit68.

<Twelfth Configuration of Pixel 51>

FIG. 35 is a cross-sectional view illustrating the twelfth configurationof the pixel 51.

The pixel 51 of the twelfth configuration illustrated in FIG. 35 is whatthe configuration of the pixel 51 illustrated in FIG. 24 is changed tothe configuration using the photoelectric conversion film 241.

That is, in the pixel structure of the pixel 51 of the twelfthconfiguration illustrated in FIG. 35 , the photoelectric conversion film241 is newly formed at the substrate back side in the same way as thesixth configuration illustrated in FIG. 17 , and the n region 82B ofFIG. 24 is omitted. Also, as the photoelectric conversion film 241functions as a shading film as well, the shading film 181 is omitted inthe pixel 51 of the twelfth configuration illustrated in FIG. 35 .Further, the photoelectric conversion film 241 of each pixel 51 isseparated by the p+ region 242.

<Thirteenth Configuration of Pixel 51>

FIG. 36 is a cross-sectional view illustrating the thirteenthconfiguration of the pixel 51.

The pixel 51 of the thirteenth configuration illustrated in FIG. 36 iswhat the configuration of the pixel 51 illustrated in FIG. 32 is changedto the configuration using the photoelectric conversion film 241.

That is, in the pixel structure of the pixel 51 of the thirteenthconfiguration illustrated in FIG. 36 , the photoelectric conversion film241 is newly formed at the substrate back side, and the n region 82B ofFIG. 32 is omitted. Also, as the photoelectric conversion film 241functions as a shading film as well, the shading film 181 is omitted inthe pixel 51 of the thirteenth configuration illustrated in FIG. 36 .Further, the photoelectric conversion film 241 of each pixel 51 isseparated by the p+ region 242.

<Manufacturing Method of Pixel 51 of Seventh Configuration>

Next, with reference to FIGS. 37A, 37B, 37C, and 37D to FIG. 39 , themanufacturing method of the pixel 51 of the seventh configurationillustrated in FIG. 24 will be described.

First, as illustrated in FIG. 37A, the photo diode 61 consisting of thep+ region 81 and the n-type semiconductor region 82 is formed in thep-type semiconductor substrate 71. The n-type semiconductor region 82 isconfigured by the n+ region 82A that is close to the p+ region 81 andthe n region 82B that is close to the back side of the semiconductorsubstrate 71.

Although, in the present embodiment, the p-type semiconductor substrate71 is used, it may be such that a p-type well region (P-Well) is formedin the n-type semiconductor substrate, using the n-type semiconductorsubstrate, and the photo diode 61 is formed in the well region.

Thereafter, as illustrated in FIG. 37 B, a p-type silicon layer ofapproximately 0.5 to 1.5 μm is formed by the epitaxial growth on thephoto diode 61.

Thereafter, as illustrated in FIG. 37 C, respective gate electrodes ofthe first transfer transistor 62, the second transfer transistor 67, andthe discharge transistor 69 are formed on the substrate surface.

Specifically, the p-type layer of the upper side than the photo diode 61in the region in which the first transfer transistor 62 and thedischarge transistor 69 are formed is etched by the dry etching methodto be removed. Then, ion of p-type, such as boron, for example is doped,at the part which forms the bottom face of the removed region, to formthe p− region 86. Further, after the gate insulating films 342 and 344and the gate insulating film 146 are formed with a silicon dioxide filmor the like on the inner wall of the etched and removed region, thepolysilicon is embedded to form the gate electrode 341 of the firsttransfer transistor 62 and the gate electrode 343 of the dischargetransistor 69 in parallel.

Also, the gate electrode 143 of the second transfer transistor 67 andothers are formed simultaneously.

Thereafter, as illustrated in FIG. 37 D, for example, the p+ region 345between the gate electrode 341 of the first transfer transistor 62 andthe gate electrode 343 of the discharge transistor 69, and thesource-drain region of each transistor such as the n+ region 147 of thedischarge transistor 69 are formed on the surface of the semiconductorsubstrate 71. Also, the n+ region 141 as the memory unit 68 and thep-type layer 142 on the top face are formed.

Thereafter, as illustrated in FIG. 38A, a connection wire layer 303including a plurality of interlayer films 301 and a plurality of metallines 302 made of tungsten, aluminium, or the like is formed at thefront side of the semiconductor substrate 71.

Then, as illustrated in FIG. 38 B, after a support substrate 304 ispasted at the upper portion of the connection wire layer 303, the backside of the semiconductor substrate 71 is polished to make the depth tothe photo diode 61 at approximately 1 μm to 5 μm, in order to make it athin film.

Thereafter, as illustrated in FIG. 39 , the shading film 181, theflattening film 90, the color filter 91, and the on-chip lens (OCL) 92are formed in this order, at the thinned back side of the semiconductorsubstrate 71.

The pixel 51 of the seventh configuration is produced by the aboveprocesses.

<Manufacturing Method of Pixel 51 of Tenth Configuration>

Next, with reference to FIGS. 40A, 40B, and 40C, the manufacturingmethod of the gate electrode of the pixel 51 of the tenth configurationof FIG. 32 which employs a V-shaped gate structure will be described.

First, as illustrated in FIG. 40A, after the photo diode 61 consistingof the p+ region 81 and the n-type semiconductor region 82 are formed inthe p-type semiconductor substrate 71, the p-type silicon layer ofapproximately 0.5 to 1.5 μm is formed on the photo diode 61 by theepitaxial growth.

Thereafter, as illustrated in FIG. 40 B, the p-type layer of the upperside than the photo diode 61 of the region in which the first transfertransistor 62 and the discharge transistor 69 are formed in a V-shapedand etched by the dry etching method to be removed. Then, ion of p-type,such as boron for example, is doped in the part which forms the bottomface of the removed region, to form the p− region 86.

Thereafter, as illustrated in FIG. 40 C, the gate insulating films 402and 404 are formed in the removed V-shaped region of the semiconductorsubstrate 71, using the thermal oxidation method or the depositionmethod, and thereafter the gate electrode 401 of the first transfertransistor 62 and the gate electrode 403 of the discharge transistor 69are further formed. The gate electrode 401 of the first transfertransistor 62 and the gate electrode 403 of the discharge transistor 69are created by forming polysilicon which is the material, patterning inthe gate electrode shape using the photolithography method, and dryetching.

Also, other transistors in which the polysilicon is formed on only thesurface of the semiconductor substrate 71, such as the gate electrode143 of the second transfer transistor 67, are formed simultaneously.

Thereafter, for example, the source-drain region of each transistor suchas the n+ region 147 of the discharge transistor 69, and the n+ region141 as the memory unit 68 and the p-type layer 142 on the top face, areformed on the surface of the semiconductor substrate 71.

The following manufacturing method is same as the method described withreference to FIGS. 38 and 39 .

In the seventh to thirteenth configurations of the above pixel 51, thegate electrode 341 (or 401) of the first transfer transistor 62 and thegate electrode 343 (or 403) of the discharge transistor 69 are locatedat the part where the carrier energy of the photo diode 61 becomeslowest. Thereby, the electric charge accumulated in the photo diode 61is transferred efficiently, when transferred to either one of the memoryunit 68 and the n+ region 147.

Note that the part where the carrier energy of the photo diode 61becomes lowest corresponds to the part where the electric potentialbecomes highest in the above structure of a solid state image sensor inwhich electron is signal electric charge, and corresponds to the partwhere the electric potential becomes lowest in the structure of a solidstate image sensor in which electron hole (hole) is signal electriccharge.

Also, in the above example, when the ion is doped uniformly in thecreation region of the photo diode 61 in the plan view direction, thecenter portion of the photo diode 61 is the part where the carrierenergy becomes lowest, and therefore the gate electrode 341 (or 401) ofthe first transfer transistor 62 and the gate electrode 343 (or 403) ofthe discharge transistor 69 are located at the position.

However, in the process for forming the photo diode 61, a predeterminedposition other than the center portion of the photo diode 61 may be setas the part where the carrier energy becomes lowest, by changing theconcentration distribution of the impurity concentration of the n-typesemiconductor region 82. Thus, the gate electrode 341 (or 401) of thefirst transfer transistor 62 and the gate electrode 343 (or 403) of thedischarge transistor 69 are located at desired positions.

Also, in the above example, the solid state image sensing device inwhich the first conductivity type is the p type, and the secondconductivity type is n type, and the electron is the signal electriccharge has been described, but the present technology may be applied toa solid state image sensing device in which the electron hole is thesignal electric charge. That is, each aforementioned semiconductorregion may be configured by the semiconductor region of the oppositeconductivity type in which the first conductivity type is n type, andthe second conductivity type is p type.

<Exemplary Configuration of Electronic Device Employing PresentTechnology>

Further, the present technology is not limited to the application to thesolid state image sensor. That is, the present technology is generallyapplicable to an electronic device using a solid state image sensor inan image acquiring unit (photoelectric conversion unit), including animage sensing device such as a digital still camera and a video camera,a portable terminal device having an image sensing function, and a copymachine using a solid state image sensor in an image reading unit. Thesolid state image sensor may be formed as one chip, or may be formed ina module having an image sensing function in which the imaging unit andthe signal processing unit or the optical system are packaged together.

FIG. 41 is a block diagram illustrating the exemplary configuration ofthe image sensing device, as the electronic device employing the presenttechnology.

An image sensing device 500 of FIG. 41 includes an optical unit 501consisting of a lens group and others, a solid state image sensor(imaging device) 502 employing each configuration of the above pixel 51,and a digital signal processor (DSP) circuit 503 which is a camerasignal processing circuit. Also, the image sensing device 500 includes aframe memory 504, a display unit 505, a record unit 506, an operationunit 507, and a power supply unit 508. The DSP circuit 503, the framememory 504, the display unit 505, the record unit 506, the operationunit 507, and the power supply unit 508 are connected to each other viaa bus line 509.

The optical unit 501 receives an incident light (image light) from asubject, and forms an image on the image capturing face of the solidstate image sensor 502. The solid state image sensor 502 converts thelight amount of the incident light for which an image is formed on theimage capturing face by the optical unit 501, to the electrical signalfor each pixel, and outputs it as a pixel signal. As this solid stateimage sensor 502, the solid state image sensor 41 of FIG. 3 may be used.

The display unit 505 is, for example, a panel display device, such as aliquid crystal panel and an organic electro luminescence (EL) panel, anddisplays a moving image or a still image captured by the solid stateimage sensor 502. The record unit 506 records the moving image or thestill image captured by the solid state image sensor 502, in a recordingmedium, such as a hard disk and a semiconductor memory.

Under the operation by a user, the operation unit 507 issues anoperation instruction with respect to various functions of the imagesensing device 500. The power supply unit 508 provides various types ofpower supply as the operation power supply of the DSP circuit 503, theframe memory 504, the display unit 505, the record unit 506, and theoperation unit 507, to these supply targets as appropriate.

Also, the present technology is not limited to the application to thesolid state image sensor that detects and captures the distribution ofthe incident light amount of the visible light as an image, but may begenerally applicable to solid state image sensors (physical quantitydistribution detecting devices), such as a solid state image sensor thatcaptures the image of the distribution of incident amount of infraredray, X ray, particles, and the like, and a fingerprint detection sensorthat detects and captures the distribution of other physical quantitiessuch as pressure and electrostatic capacitance as an image, in a broadsense.

The embodiments of the present technology are not limited to the aboveembodiments, but may be variously changed in a scope not departing fromthe spirit of the present technology, e.g., parts of configurations ofthe above pixels may be combined as necessary as appropriate.

Additionally, the present technology may also be configured as below.

(1)

A solid state image sensor including:

a photoelectric conversion unit formed and embedded in a semiconductorsubstrate;

an impurity region that retains an electric charge generated by thephotoelectric conversion unit; and

a transfer transistor that transfers the electric charge to the impurityregion,

wherein a gate electrode of the transfer transistor is formed in a depthdirection toward the photoelectric conversion unit in the semiconductorsubstrate, from a surface of the semiconductor substrate on which theimpurity region is formed, and

wherein a channel portion of the transfer transistor is surrounded bythe gate electrode in two or more directions other than a direction ofthe impurity region, as seen from the depth direction.

(2)

The solid state image sensor according to (1), wherein

the photoelectric conversion unit is a photo diode, and

the gate electrode of the transfer transistor is formed to a positionidentical with a p-n junction plane of the photo diode or deeper thanthe p-n junction plane.

(3)

The solid state image sensor according to (1) or (2), wherein

an impurity concentration of the channel portion of the transfertransistor surrounded by the gate electrode in two or more directions islower than an impurity concentration at an outside of the gateelectrode.

(4)

The solid state image sensor according to any of (1) to (3), wherein

a separation region is formed by an insulator, in an opposite region tothe impurity region, as seen from the gate electrode.

(5)

The solid state image sensor according to any of (1) to (4), wherein

the gate electrode of the transfer transistor is formed in a U shapewhich opens in a direction of the impurity region, as seen from thedepth direction.

(6)

The solid state image sensor according to any of (1) to (5), wherein

the impurity region is a memory unit that temporarily retains theelectric charge before transferring the electric charge to a floatingdiffusion region, and

in an upper portion of the memory unit, a gate electrode to which apredetermined voltage is applied is formed, in addition to the gateelectrode of the transfer transistor.

(7)

A manufacturing method of a solid state image sensor, the manufacturingmethod including the steps of:

forming a photoelectric conversion unit by embedding the photoelectricconversion unit in a semiconductor substrate;

forming a gate electrode of a transfer transistor that transfers anelectric charge generated by the photoelectric conversion unit, in adepth direction toward the photoelectric conversion unit in thesemiconductor substrate, from a surface of the semiconductor substrate;and

forming an impurity region that retains the electric charge transferredby the transfer transistor, on the surface of the semiconductorsubstrate,

wherein a channel portion of the transfer transistor is surrounded bythe gate electrode in two or more directions other than a direction ofthe impurity region, as seen from the depth direction.

(8)

An electronic device including:

a solid state image sensor including

-   -   a photoelectric conversion unit formed and embedded in a        semiconductor substrate,    -   an impurity region that retains an electric charge generated by        the photoelectric conversion unit, and    -   a transfer transistor that transfers the electric charge to the        impurity region,    -   wherein a gate electrode of the transfer transistor is formed in        a depth direction toward the photoelectric conversion unit in        the semiconductor substrate, from a surface of the semiconductor        substrate on which the impurity region is formed, and    -   wherein a channel portion of the transfer transistor is        surrounded by the gate electrode in two or more directions other        than a direction of the impurity region, as seen from the depth        direction.        (9)

A solid state image sensor including:

a photoelectric conversion unit formed and embedded in a semiconductorsubstrate;

a memory unit that retains an electric charge generated by thephotoelectric conversion unit;

a transfer transistor that transfers the electric charge to the memoryunit; and

a discharge transistor that discharges an unnecessary electric chargegenerated by the photoelectric conversion unit,

wherein a gate electrode of the transfer transistor and a gate electrodeof the discharge transistor are adjacent to each other in parallel in adepth direction of the semiconductor substrate, via an insulating filmor an impurity region having a higher impurity concentration than achannel portion which forms an electrical current path.

(10)

The solid state image sensor according to (9), wherein

the photoelectric conversion unit is a photo diode, and

the gate electrodes of the transfer transistor and the dischargetransistor are formed to a position identical with a p-n junction planeof the photo diode or deeper than the p-n junction plane.

(11)

The solid state image sensor according to (10), wherein

the gate electrodes of the transfer transistor and the dischargetransistor are connected to a part at which a carrier energy becomeslowest on a formation plane of the photo-diode.

(12)

The solid state image sensor according to any of (9) to (11), wherein

a photoelectric conversion film formed with a material having a largerlight absorption coefficient than the semiconductor substrate is locatedat a back side of the semiconductor substrate.

(13)

A manufacturing method of a solid state image sensor, the manufacturingmethod including the steps of:

forming a photoelectric conversion unit by embedding the photoelectricconversion unit in a semiconductor substrate;

forming a gate electrode of a transfer transistor that transfers to amemory unit an electric charge generated by the photoelectric conversionunit, and a gate electrode of a discharge transistor that discharges anunnecessary electric charge generated by the photoelectric conversionunit, in parallel in a depth direction from a surface of thesemiconductor substrate, toward the photoelectric conversion unit in thesemiconductor substrate; and

forming an insulating film or an impurity region having a higherimpurity concentration than a channel portion which forms an electricalcurrent path, between the gate electrode of the transfer transistor andthe gate electrode of the discharge transistor.

(14)

An electronic device including:

a solid state image sensor including

-   -   a photoelectric conversion unit formed and embedded in a        semiconductor substrate,    -   a memory unit that retains an electric charge generated by the        photoelectric conversion unit,    -   a transfer transistor that transfers the electric charge to the        memory unit, and    -   a discharge transistor that discharges an unnecessary electric        charge generated by the photoelectric conversion unit,    -   wherein a gate electrode of the transfer transistor and a gate        electrode of the discharge transistor are adjacent to each other        in parallel in a depth direction of the semiconductor substrate,        via an insulating film or an impurity region having a higher        impurity concentration than a channel portion which forms an        electrical current path.        (15)

A solid state image sensor including:

a photoelectric conversion unit formed and embedded in a semiconductorsubstrate;

a memory unit that retains an electric charge generated by thephotoelectric conversion unit;

a transfer transistor that transfers the electric charge to the memoryunit; and

a discharge transistor that discharges an unnecessary electric chargegenerated by the photoelectric conversion unit,

wherein end portions, close to the photoelectric conversion unit, of agate electrode of the transfer transistor and a gate electrode of thedischarge transistor are located at adjacent positions in a formationplane of the photoelectric conversion unit, and

wherein as a depth from a surface of the semiconductor substrate becomesshallower, the gate electrode of the transfer transistor and the gateelectrode of the discharge transistor gradually get away from eachother.

(16)

The solid state image sensor according to (15), wherein

the photoelectric conversion unit is a photo diode, and

the gate electrodes of the transfer transistor and the dischargetransistor are formed to a position identical with a p-n junction planeof the photo diode or deeper than the p-n junction plane.

(17)

The solid state image sensor according to (16), wherein

the gate electrodes of the transfer transistor and the dischargetransistor are connected to a part at which a carrier energy becomeslowest on a formation plane of the photo-diode.

(18)

The solid state image sensor according to any of (15) to (17), wherein

a photoelectric conversion film formed with a material having a largerlight absorption coefficient than the semiconductor substrate is locatedat a back side of the semiconductor substrate.

(19)

A manufacturing method of a solid state image sensor, the manufacturingmethod including the steps of:

forming a photoelectric conversion unit by embedding the photoelectricconversion unit in a semiconductor substrate; and

forming a gate electrode of a transfer transistor that transfers to amemory unit an electric charge generated by the photoelectric conversionunit, and a gate electrode of a discharge transistor that discharges anunnecessary electric charge generated by the photoelectric conversionunit, in a depth direction from a surface of the semiconductorsubstrate, toward the photoelectric conversion unit in the semiconductorsubstrate,

wherein end portions, close to the photoelectric conversion unit, of thegate electrode of the transfer transistor and the gate electrode of thedischarge transistor are located at adjacent positions in a formationplane of the photoelectric conversion unit, and

wherein as a depth from the surface of the semiconductor substratebecomes shallower, the gate electrode of the transfer transistor and thegate electrode of the discharge transistor gradually get away from eachother.

(20)

An electronic device including:

a solid state image sensor including

-   -   a photoelectric conversion unit formed and embedded in a        semiconductor substrate,    -   a memory unit that retains an electric charge generated by the        photoelectric conversion unit,    -   a transfer transistor that transfers the electric charge to the        memory unit, and    -   a discharge transistor that discharges an unnecessary electric        charge generated by the photoelectric conversion unit,    -   wherein end portions, close to the photoelectric conversion        unit, of a gate electrode of the transfer transistor and a gate        electrode of the discharge transistor are located at adjacent        positions in a formation plane of the photoelectric conversion        unit, and    -   wherein as a depth from a surface of the semiconductor substrate        becomes shallower, the gate electrode of the transfer transistor        and the gate electrode of the discharge transistor gradually get        away from each other.

REFERENCE SIGNS LIST

-   41 solid state image sensor-   44 pixel array unit-   51 pixel-   61 photo diode-   62 transfer transistor-   63 FD (floating diffusion region)-   64 reset transistor-   68 memory unit (MEM)-   69 discharge transistor-   71 semiconductor substrate-   83 n+ region-   84 gate electrode-   89 separation region-   121 p+ region-   201 gate electrode-   241 photoelectric conversion film-   343 gate electrode-   361 separation region-   500 image sensing device-   502 solid state image sensor

What is claimed is:
 1. A solid state image sensor, comprising: aphotoelectric conversion unit configured to generate an electric charge,wherein the photoelectric conversion unit is embedded in a semiconductorsubstrate; an impurity region configured to retain the generatedelectric charge; a transfer transistor configured to transfer theelectric charge to the impurity region; and a discharge transistorconfigured to discharge an unnecessary electric charge generated by thephotoelectric conversion unit, wherein a gate electrode of the transfertransistor is adjacent to a gate electrode of the discharge transistorin a depth direction of the semiconductor substrate.
 2. The solid stateimage sensor according to claim 1, wherein the gate electrode of thetransfer transistor is adjacent to the gate electrode of the dischargetransistor in parallel in the depth direction of the semiconductorsubstrate, via an insulating film.
 3. The solid state image sensoraccording to claim 1, wherein the photoelectric conversion unit is aphoto diode.
 4. The solid state image sensor according to claim 3,wherein the gate electrode of the transfer transistor and the gateelectrode of the discharge transistor are in a position identical with ap-n junction plane of the photo diode.
 5. The solid state image sensoraccording to claim 3, wherein the gate electrode of the transfertransistor and the gate electrode of the discharge transistor are in aposition deeper than a p-n junction plane of the photo diode.
 6. Thesolid state image sensor according to claim 1, wherein the gateelectrode of each of the transfer transistor and the dischargetransistor is connected to a part at which a carrier energy is lowest ona formation plane of a photo-diode of the photoelectric conversion unit.7. The solid state image sensor according to claim 1, further comprisinga photoelectric conversion film including a material having a largerlight absorption coefficient than the semiconductor substrate, whereinthe photoelectric conversion film is located at a back side of thesemiconductor substrate.
 8. The solid state image sensor according toclaim 1, further comprising a channel portion including an electricalcurrent path between the gate electrode of the transfer transistor andthe gate electrode of the discharge transistor.
 9. The solid state imagesensor according to claim 8, wherein an impurity concentration at theimpurity region is higher as compared to an impurity concentration atthe channel portion.
 10. An electronic device, comprising: a solid stateimage sensor including: a photoelectric conversion unit configured togenerate an electric charge, wherein the photoelectric conversion unitis embedded in a semiconductor substrate; an impurity region configuredto retain the generated electric charge; a transfer transistorconfigured to transfer the electric charge to the impurity region; and adischarge transistor configured to discharge an unnecessary electriccharge generated by the photoelectric conversion unit, wherein a gateelectrode of the transfer transistor is adjacent to a gate electrode ofthe discharge transistor in a depth direction of the semiconductorsubstrate.
 11. The electronic device according to claim 10, wherein thegate electrode of the transfer transistor is adjacent to the gateelectrode of the discharge transistor in parallel in the depth directionof the semiconductor substrate, via an insulating film.
 12. Theelectronic device according to claim 10, further comprising a channelportion including an electrical current path between the gate electrodeof the transfer transistor and the gate electrode of the dischargetransistor.
 13. The electronic device according to claim 12, wherein animpurity concentration at the impurity region is higher as compared toan impurity concentration at the channel portion.
 14. The electronicdevice according to claim 10, wherein the photoelectric conversion unitis a photo diode.
 15. The electronic device according to claim 14,wherein the gate electrode of the transfer transistor and the gateelectrode of the discharge transistor are in a position identical with ap-n junction plane of the photo diode.
 16. The electronic deviceaccording to claim 14, wherein the gate electrode of the transfertransistor and the gate electrode of the discharge transistor are in aposition deeper than a p-n junction plane of the photo diode.
 17. Theelectronic device according to claim 10, wherein the gate electrode ofeach of the transfer transistor and the discharge transistor isconnected to a part at which a carrier energy is lowest on a formationplane of a photo-diode of the photoelectric conversion unit.
 18. Theelectronic device according to claim 10, wherein the solid state imagesensor further includes a photoelectric conversion film including amaterial having a larger light absorption coefficient than thesemiconductor substrate, and the photoelectric conversion film islocated at a back side of the semiconductor substrate.
 19. A solid stateimage sensor, comprising: a photoelectric conversion unit configured togenerate an electric charge, wherein the photoelectric conversion unitis embedded in a semiconductor substrate; an impurity region configuredto retain the generated electric charge; a transfer transistorconfigured to transfer the electric charge to the impurity region; and adischarge transistor configured to discharge an unnecessary electriccharge generated by the photoelectric conversion unit, wherein endportions, close to the photoelectric conversion unit, of a gateelectrode of the transfer transistor is adjacent to a gate electrode ofthe discharge transistor are in a formation plane of the photoelectricconversion unit, and a distance between the gate electrode of thetransfer transistor and the gate electrode of the discharge transistorgradually increases as a depth from a surface of the semiconductorsubstrate becomes shallower.